組合語言第一次作業

作業內容：

Basic:

Complete the following table. 10%

-7239₁₀	16-bit Binary	16-bit Hexadecimal
Sign Extension	1	F
1's Complement	1110001110111000	FFFFE3B8
2's Complement	1110001110111001	FFFFE3B9

Perform the following, using 8-bit binary and 2's complement numbering system. 10%

(1) 23 + (-59) = ? 11011100

(2) (-13) * ( -8 ) = ? 01101000

Please state what you learn after trying "debug" or "MASM". 20%

After trying 'debug', I learned how to check the status of CPU's registers, assemble/desamble codes, and run the codes.
I also learn how to use 'interrupt' that system provides.
'debug' provides following commands:

command syntex explaination

Go g[=start] [end] run from start to end

Unassembel u[=start] desamble codes from start

Trace t[=address] [n] execute code at address for n instr.

Procedure exec. p trace over code

Name n[file name] set the file name

Write w write coeds to disk with length (BX,CX)

Display d[start] [end] display memory from start to end

Register info. r show the info of all registers

Modify register value r[register] modify the value of register

Advanced: 60%

Please collect as more the information of the addressing modes used in 80X86 or other PC system as possible. You can state their histories, characters, performances, and so on. Please find them out in the internet or at library.

CISC MACHINES

Complex Instruction Set Computers
This kind of machines generally have a relatively large and complicated instruction set, several different instruction formats and lengths, and addressing modes.
1. VAX Architecture
The VAX family of computers was introduced by Digital Equipment Corporation (DEC) in 1978. The VAX architecture was provided for compatiblity with the earlier PDP-11 amchines.
The VAX memory consists of 8-bit byte.

Type byte word longword quadword octaword

Length 8-bit 2 byte 4 byte 8 byte 16 byte

VAX provides a large number of addressing modes:

register mode

register deferred mode

autoincrement/autodecrement modes

2. x86 Architecture
The earliest processor of x86 family is 8086, intriduced by Intel Corp. in 1978.
At physical level, x86 memory consists 8-bit bytes.

Type byte word double word

Length 8-bit 2 byte 4 byte

For I/O Address Space, x86 accessible I/O size is 64KByte and can be accessed through 8-bit, 16-bit or 32-bit ports

Processor register width data line address line

8086 16 16 20

8088 16 8 20

80286 16 16 24

80386DX 32 32 32

80386SX 32 16 24

80486 32 32 32

Pentium 32 64 32

The x86 architecture provides a large number of addressing modes.

Real Mode Memory Addressing

Due to upward compatibility, x86 CPU can only addresses the lowest 1MByte of memory in real mode. To calculate a physical memory address, the 16-bit segment base address located in the selected segment register is multiplied by 16 and then the 16-bit offset address is added.
TA=(base register)+(index register)*(scale factor)+displacement

Protect Mode Memory Addressing

In protected mode three mechanisms calculate a physical memory address

Offset Mechanism which produces the offset or effective address as in real mode.

Selector Mechanism Using segmentation, memory is divided into an arbitrary number of segments, each containing usually much less than the 2³² byte (4 GByte) maximum.

Paging Mechanism The page size is always 4 KBytes. The paging mechanism translates the 20 most significant bits of a linear address to a physical address.

Reference link: IBM 486, 5x86, and 6x86 microprocessor User's Manuals. / MultiProcessor Specification. Intel Corp. 1994.

RISC MACHINES

Reduced Instruction Set Computers in contrast to traditional CISC implementions.
In general, a RISC system is characterized by a standard, fixed instruction length, a single-cycle execution of most instructions. There are typically a relatively large number of general-purpose registers, since instructions except for load and store are register-to-register operations.
1. UltraSPARC Architecture
The UltraSPARC processor, announced by Sun Microsystems in 1995, is one of the SPARC family including a varity of SPARC and SuperSPARC.
Memory consists of 8-bit bytes; all addresses used are byte addresses.

Type byte halfword word double word

Length 8-bit 2 byte 4 byte 8 byte

UltraSPAEC programs can be written using a virtual address space of 2⁶⁴ bytes. This address space is divided into pages; multiple page sizes are supported. The virtual address specified by the instruction is automatically translated into a physical address by the UltraSPARC Memory Management Unit (MMU).
As in most architectures, an operand value may be specified as part of the instruction itself (immediate mode), or it may be in a register (register direct mode). Operands in memory are addressed using one of the following three modes:

Mode Target Address

PC-relative TA=(PC)+displacement(30bits, sigened)

Register indirect with displacement TA=(register)+deiplacement(13bits,signed)

Register indirect indexed TA=(register1)+(register2)

PC-relative mode is only for branch instructions.
Reference link: Sun Microsystem
(There is one interesting product is picoJava chip here...!!! A hardware implemention of JVM.)
2. PowerPC Architecture
IBM first introduced the POWER architecture early in 1990 with the RS/6000. (POWER is an acronym for Performance Optimization With Enhanced RISC.)
The memory consists of 8-bit byte; all addresses used are byte addresses.

Type byte halfword word doubleword quadword

Length 8-bit 2 byte 4 byte 8 byte 16 byte

The PowerPC 750 implements the memory management specification of the PowerPC OEA for 32-bit implementations. Thus, it provides 4 Gbytes of effective address space accessible to supervisor and user programs, with a 4-Kbyte page size and 256-Mbyte segment size.
As in most architectures, an operand value may be specified as part of the instruction itself (immediate mode), or it may be in a register (register direct mode).
The only instructions that address memory are load and store operations, and branch instructions.

Load and store operations use one of the following three modes:

Mode Target Address

Register indirect TA=(register)

Register indirect with index TA=(register1)+(register2)

Register indirect with immediate indexed TA=(register)+deiplacement(16bits,signed)

The register numbers and displacement are encoded as part of the instruction.
Branch instructions use one of the following three modes:

Mode Target Address

Absolute PC- TA=actual address(PC)+displacement(30bits, sigened)

Relative TA=current intruction address +deiplacement(25bits,signed)

Link Register TA=(LR)

Count Register TA=(CR)

Reference link: IBM PoertPC RISC microprocessor User's Manuals, Technical Summaries and Hardware

1.3 Cray T3E Architecture
The T3E series of supercomputers was announced by Cray Research, Inc., near the end of 1995. The T3E is a massively parallel processing (MPP) system, designed for use on technical applications in scientific computing.
A T3E system contains a large number of processing elements (PE), arranged in a 3D network. Each PE consists of a DEC Alpha EV5 RISC microprocessor. (currently model 21164).
The basic addressable unit in the Alpha architecture is the 8-bit byte. The 21164PC supports a 43-bit virtual address. Virtual addresses as seen by the program are translated into physical memory addresses by the memory-management mechanism. The 21164PC supports a 40-bit uncached and a 33-bit cached physical address space.
The MTU receives up to two virtual addresses every cycle from the IEU. The trans-lation buffer generates the corresponding physical addresses and access control information for each virtual address. The 21164PC implements a 43-bit virtual address, a 40-bit noncacheable physical address, and a 33-bit cacheable physical address. Cacheable addresses consist of bits <32:0> when bit <39> = 0. Physical addresses that set bits <38:33> are not supported by the 21164PC. These addresses are not checked by the 21164PC and could result in erroneous data.
As in most architectures, an operand value may be specified as part of the instruction itself (immediate mode), or it may be in a register (register direct mode).
The only instructions that address memory are load and store operations, and branch instructions.

Operands in memory are addressed using one of the following three modes:

Mode Target Address

PC-relative TA=(PC)+deiplacement(23bits, signed)

Register indirect with displacement TA=(register)+deiplacement(16bits,signed)

Register indirect with displacement mode is used for load and store operations and for subroutine jumps. PC-relative mode is used for conditional and unconditional branches.
Reference link: Digital Semiconductor Alpha 21164 PC Microcessor Hardware Reference Manual

Reference:
System Software, An introduction to systems programing 3rd. Edition / Leland L. Beck / Addison Wesley

command	syntex	explaination
Go	g[=start] [end]	run from start to end
Unassembel	u[=start]	desamble codes from start
Trace	t[=address] [n]	execute code at address for n instr.
Procedure exec.	p	trace over code
Name	n[file name]	set the file name
Write	w	write coeds to disk with length (BX,CX)
Display	d[start] [end]	display memory from start to end
Register info.	r	show the info of all registers
Modify register value	r[register]	modify the value of register

Type	byte	word	longword	quadword	octaword
Length	8-bit	2 byte	4 byte	8 byte	16 byte

Processor	register width	data line	address line
8086	16	16	20
8088	16	8	20
80286	16	16	24
80386DX	32	32	32
80386SX	32	16	24
80486	32	32	32
Pentium	32	64	32

Offset Mechanism	which produces the offset or effective address as in real mode.
Selector Mechanism	Using segmentation, memory is divided into an arbitrary number of segments, each containing usually much less than the 2³² byte (4 GByte) maximum.
Paging Mechanism	The page size is always 4 KBytes. The paging mechanism translates the 20 most significant bits of a linear address to a physical address.

Type	byte	halfword	word	double word
Length	8-bit	2 byte	4 byte	8 byte

Mode	Target Address
PC-relative	TA=(PC)+displacement(30bits, sigened)
Register indirect with displacement	TA=(register)+deiplacement(13bits,signed)
Register indirect indexed	TA=(register1)+(register2)

Mode	Target Address
Register indirect	TA=(register)
Register indirect with index	TA=(register1)+(register2)
Register indirect with immediate indexed	TA=(register)+deiplacement(16bits,signed)

Mode	Target Address
Absolute PC-	TA=actual address(PC)+displacement(30bits, sigened)
Relative	TA=current intruction address +deiplacement(25bits,signed)
Link Register	TA=(LR)
Count Register	TA=(CR)

組合語言第一次作業

作業內容：

Basic:

Complete the following table. 10%

-723910

16-bit Binary

16-bit Hexadecimal

Sign Extension

1

F

1's Complement

1110001110111000

FFFFE3B8

2's Complement

1110001110111001

FFFFE3B9

Perform the following, using 8-bit binary and 2's complement numbering system. 10%

(1) 23 + (-59) = ? 11011100

(2) (-13) * ( -8 ) = ? 01101000

Please state what you learn after trying "debug" or "MASM". 20%

Advanced: 60%

Please collect as more the information of the addressing modes used in 80X86 or other PC system as possible. You can state their histories, characters, performances, and so on. Please find them out in the internet or at library.

-7239₁₀